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correct by construction

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Esterel EDA

ESL-to-RTL synthesis for control-intensive IP design and verification.

RTL

VHDL

Verilog

code generation

SystemC

formal methods

correct by construction

ESL synthesis

automated implementation

Electronic System Level

unambiguous specifications

Esterel Studio

www.esterel-eda.com - 2009-02-09

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